The well known and characterized nature of DRAM memory cells to leak charge used to represent stored logic values requires the cells to be regularly and periodically refreshed (read and re-written). If the cells are not refreshed before the charge level diminishes significantly, data loss may result. During the time consumed by a DRAM refresh operation, the portion of the memory (DIMM, chip, or rank) being refreshed becomes unavailable for normal read and write operations, rendering it unusable during that period of time.
A convergence of ongoing trends in DRAM design and usage have caused an increase in the total amount of time required for refresh, relative to the total amount of time the memory is available for read/write operations. These trends include increased memory capacity per system, increased memory density per chip, the need to limit chip power supply noise, higher leakage rates in shrinking chip technologies, and shorter refresh intervals.
Because processor access to data contained in DRAM memory is a critical factor in overall computer system performance, workload and application throughput can be limited by the decreasing fraction of time that DRAM memory is available for read and write operations. The introduction of DDR4 memory devices included a number of options to change both DRAM refresh interval timing, as well as the amount of time taken for each refresh operation. These options may be selected at any point in time, for example on system boot-up. However, a fixed DRAM refresh setting may not yield appropriate or suitable memory system throughput characteristics for a workload which may change over time.